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  1. Status Register

    The status register is an internal register reflecting processor state. Most instructions are modifiying state of some bits in this register. The whole register can be read and written with rsr and wsr instructions. Individual arithmetic bits can be tested with conditionnal jump instructions.

    STATUS REGISTER














    2
    4






















    1
    2






    0
    8













    0
    0
    0 0 0 0 I I I I 0 0 0 0 0 0 0 0 0 0 S S R R R R 0
    0
    0
    0
    C V N Z

    Arithmetic operation result flags

    These flags are set after execution of arithmetic instructions. Their state reflect results of these operations.

    Z = Zero Flag. Set when last instruction result is zero. State of this flag can be tested with beq and bne conditionnal instructions.
    N = Negative Flag. Set when last instruction result is negative. This mean the most significant bit is set to 1. State of this flag can be tested with bmi and bpl conditionnal instructions.
    V = Overflow Flag. Set when overflow occured in signed arithmetic operation. State of this flag can be tested with bvc and bvs conditionnal instructions.
    C = Carry Flag. Set when overflow occured in unsigned arithmetic operation. State of this flag can be tested with bcc and bcs conditionnal instructions.

    Processor state flags

    R= 4 bits : The last register used in indexed move operation.
    S = 2 bits : Register stepping related to latest indexed move operation. 00 = 1 byte, 01 = 2 bytes, 10 = 4 bytes, 11 = 8 bytes.
    I = 4 bits : Actual interrupt priority level. Only interrupts of higher level can be triggered. When interruption occur, the level of the interrupt is set in these fields. Setting this to 1111 disables interrupts.

    Unused flags

    Don't set or clear any unused bits as these can get some functions in further evolutions.

     

     
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